The Latest Progress of VCSEL-based CPO

At present, most CPO products are based on silicon optical solutions, but VCSEL has obvious advantages in cost and power consumption in ultra-short distance transmission.

FiberMall will introduce the latest progress of VCSEL-based CPO from four companies, IBM, HPE, Fujitsu, and Furukawa, in the following.

IBM

In cooperation with II-VI, IBM undertook the U.S. Department of Energy (ARPA-E) project, MOTION (Multi-wavelength Optical Transceiver Integrated ON NODE). The project is divided into two phases, Phase 1 and Phase 2, and the specifications of the two phases are shown in the figure below, the main difference is the number of channels, the rate, the electrical chip, etc. The size of the CPO module remains the same.

The VCSEL wavelength is 940nm and can reach a rate of 56Gbaud, which can support 112Gbps PAM4 signals. The electrical chip in Phase 1 is a 55nm BiCMOS process, and the Tx and Rx are two separate chips with 16 channels. The chip size is 1.64mm*4.64mm. There is no retiming function in the electric chip so that it can support low latency application scenarios. The electric chip, VCSEL, and PD chip are flip-chip to the glass substrate as shown in the figure below.

After the optical components such as lenses are packaged together, the overall module size is 13mm*13mm, comparable to the size of a coin, as shown in the figure below.

Given the CPO’s proximity to the switch chip, VCSEL performance may be affected. IBM has put redundant VCSEL on the system, as shown in the figure below, and the reliability of the whole system is increased by 1000 times. If the Primary VCSEL fails, it can quickly switch to the Spare channel.

IBM did not show many full-link results, only the 16-channel VCSEL eye diagram. 2.7pJ/bit for the Tx side, including the power consumption of the VCSEL, and 1.5pJ/bit for the Rx side, with a theoretical simulation value of 4.2pJ/bit. The bandwidth of the whole system is 800Gbps (16x50Gbps). In addition, the system uses a single wavelength VCSEL, and Phase 2 will introduce multiple wavelengths.

HPE

HPE has also been working on developing VCSEL-based CPO, and the structure of HPE’s 4-channel CPO system is shown in the figure below.

The CPO system contains 5 wavelengths of VCSEL lasers with wavelengths of 990/1015/1040/1065/1090nm. 3dB bandwidth of all 5 wavelengths is greater than 18GHz, which can support 56Gbps PAM4 signal as shown in the figure below. 990nm VCSEL has a slightly lower bandwidth. By using pre-distorted electrical signals and increasing the size of the drive current, the VCSEL can support 112Gbps PAM4 signals.

VCSEL array, PD array, and film filter are assembled together to form a four-wavelength CPO module. Because PD couldn’t match the TIA chip, HP used an external detector. The CPO module has no integrated electrical chip. The eye diagram of the CPO Tx side is shown below, and the BER is less than 1e-6.

Fujitsu

Fujitsu’s VCSEL CPO solution is shown in the figure below. 16 channels of VCSELs and PD arrays are used in the system, and the VCSELs and PDs are distributed in a circular shape with a distance of 40um between adjacent channels in order to facilitate coupling with the multicore fiber (MCF). The Driver and TIA chips are placed on the back side of the Interposer.

The CPO module adopts the electrical interface of LGA, and the pitch is 300um. In order to achieve the interconnection of high-speed electrical signals, the interposer uses 10 layers of metal, the thickness of the entire interposer is 340um. The cross-section is shown below. Both optical and electrical chips are placed on the interposer by flip chip.

The overall size of the CPO module is 7.8*16*8.0mm, which is also the same size as the coin, as shown in the figure below. The bandwidth of the CPO module is 400Gbps(25Gbps NRZ*16). Fujitsu did not give measured results for the entire link.

Furukawa

Furukawa’s VCSEL CPO solution is shown below, using two 4-channel VCSEL and PD arrays. In order to reduce the length of electrical interconnection, Driver and TIA chips are placed on both sides of VCSEL and PD respectively. Both the optical chips and the electrical chips are directly attached to the substrate, and the optical chips and the electrical chips are interconnected through wire bonding. The CPO module adopts the electrical interface form of the LGA, and the pitch of the LGA is 300um. The optical port uses MT head and contains 24 channels.

The 3dB bandwidth of VCSEL is 17GHz, and the 3dB bandwidth of PD is 23GHz, both can support 56Gbps PAM4 signal.

Furukawa built a 4.4m long link, and the BER test results are shown below. For 28Gbps NRZ signal, the optical power at the Rx end is greater than -10dBm, and the BER is less than 1e-12. For 56Gbps PAM4 signal, the optical power at the Rx end should be greater than -8dBm, and the BER is less than 2.4e-4.

The size of CPO module is 15.9*7.7*7.95mm and the total bandwidth is 448Gbps (56×8), corresponding to a bandwidth density of 7.32Gbps/mm^2 (bidirectional).

A brief comparison of the results from the four companies mentioned above is shown in the figure below.

In contrast, IBM’s VCSEL CPO has superior performance in all aspects, and its electrical chip is specially designed and developed by itself. The other three companies did not reveal much driver/TIA information in their articles. The four companies’ VCSEL CPO are still in the R&D stage, and the performance characterization of full link is not very perfect. In addition, because the system contains multiple channels of VCSEL and PD, its reliability and maintenance are challenged. It is also worth thinking about how to upgrade the bandwidth afterwards. Since the transmission distance of VCSEL is relatively short, VCSEL CPO may be mainly used in intra-rack and inter-rack signal interconnection.