PCI-E: 8 Things You Need to Know Early

1. What is PCI Express, and What does it Stand for?

According to the definition by Wikipedia, PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e, is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X, and AGP bus standards. As one of the high-speed buses within computers,  PCI-E is not only a data channel but also a network motherboard interface. The latter is the long slot part on the control panel.

 

PCIe is the most crucial bus in the server system because signals are interconnected through PCIe, enabling the CPU to achieve communication with various external devices. If we compare each bit of data to a small car, and PCIe bus is like the two-way lanes. But the PCIe specification has its own speed limit, which indicates that if there are more lanes existing, the faster the speed will be, i.e. there will be more data traffic being transmitted.

 

2. Current Status & Future Direction of PCI-E

PCIe 6.0 Base Specification has released its Draft 0.5 version so far and PCIe 6.0 standard has completed the interpretation for the 0.5 version, which is expected to be launched officially in 2021. However, the PCIe 6.0 CEM Specification is still under deliberation by the PCI-SIG.  

∆ The Blue Lane Highlights the PCIe Bus 

Meanwhile, PCIe 4.0 Ice Lake Xeon-SP CPU supported by Intel is about to release at the end of this year and the AMD EPYC CPU supporting PCIe 4.0 as well as numerous ARM CPUs is gradually on sale. As a result, PCIe 4.0 will become the mainstream on the market in 2021, prompting cable manufacturers and suppliers to think about where PCI-E cables go.

 

3. PCIe vs PCI: The Evolution and Proliferation of PCIe Gen

The PCI was born in 1992 with its PCI bus bandwidth of 133MB/S then. After that, intel raised the bus status bit to 64 at the request of transmission in the server area. Thus, 2 new PCI buses were created which were 64bit/33Mhz and 64bit/66Mhz in clock speed with a data transfer speed of 266Mbps and 533Mbps respectively.

 

In the field of graphics cards, Intel individually developed AGP(Accelerated Graphics Port) and released “AGP specification 1.0” in 1997 with a 32-bit bus operating at 66 MHz and a bandwidth of 266Mbps. The subsequent Specification AGP 2.0 documented 1.5 V signaling, which could be used at 2× and 4× and the fasted speed of 4x could reach 1Gbps.  Technically speaking, AGP is not a real bus standard for it can only connect one device, i.e. graphics card.

 

As for the application in servers, a few manufacturers and suppliers including IBM, HP, and Compaq jointly develop the PCI-X standards and got the approval in 1998. Specification 64bit 133Mhz specified that the PCI supports a maximum of 1 GB/s bandwidth in each direction.

 

Specification PCI-X 2.0 and PCI-X 3.0 have updated the clock speed from 266Mhz, through 533Mhz to even 1GMhz. But by then, there were also some problems for PCI-X. On the one hand, the parallel signal crosstalk appeared due to the clock speed increase, on the other hand, there was resource contention caused by the shared bus. In short, although the specifications are updated, the actual effect may not be able to meet these indicators.

∆ PCIe Network Interface Card

 

Thereupon, Intel officially announced its third-gen I/O technology to replace the PCI bus at the Intel Spring IDF Conference in 2001. This standard was developed by the AWG(Arapahoe Working Group) supported by Intel and was named as 3rd Generation I/O, also 3GIO.

Obviously, Intel indicated that it stands for the next-gen I/O interface specification and was not called PCI-Express until it was submitted to the PCI-SIG(PCI Special Interest Group) and got approval.

 

4. Common PCIe Slots

According to the specifications provided by PCI-SIG, there are 7 versions of PCI-E slots x1, x2, x4, x8, x12, x16, and x32, corresponding to 1/2/4/8/12/16/32 channels, of which PCI -E x32 is only used on some special occasions due to volume problems, and the corresponding mass production products are almost zero; PCI-E x12 is mainly applied in the servers; while PCI-E x2 is mainly used for internal interfaces rather than expansion slots, even if some motherboards provide this interface, its PCI -E x2 also basically appears in the form of M.2 interface, rather than the form of PCI-E slot. Physical PCI Express links may contain from 1 to 16 lanes, more precisely “PCIe x8” connections have eight data lanes. Therefore, the current mainstream PCI-E slots on motherboards are basically concentrated in four PCI-E x1/x4/x8/x16.

 

5. Advantages of PCI-E

PCI-e would replace the PCI and AGP overall and reach a united status of high-speed serial computer expansion bus standard. One of its advantageous features is the ability to transfer a big data rate, which can currently reach more than 10GB/s, and it is expected to develop to a new transmission speed level. Also, there is a variety of specifications for PCI Express from PCI Express 1X to PCI Express 16X, which can meet the needs of low-speed devices and high-speed devices that will appear in a certain period of time in the future.

 

∆ Overview of Common PCIe x1, x4, x8, x16 Slots

PCI Express (hereinafter referred to as PCI-E) devices communicate via a logical connection called an interconnect or link. A link is a point-to-point communication channel between two PCI Express ports. Compared with the shared parallel bus architecture of PCI and earlier computer buses, each PCI-E device has its own dedicated connection and does not need to request bandwidth from the entire bus. 

 

In addition, it can increase the data transfer rate to a very high frequency, and achieve a high bandwidth that a PCI device cannot reach. By contract with the traditional PCI bus that can only achieve single-direction signal transmission over a single time period, the dual-simplex connection of PCI-E can provide a higher transmission rate and quality. The difference between them is similar to half-duplex and full-duplex.

 

6 . What are the Standard PCIe Sizes?

The PCI-E interface varies according to the bus bit width, including X1, X4, X8, and X16, and the X2 mode will be used for the internal interface instead of the slot mode. The PCI-E specification ranges from 1 channel connection to 32 channel connection, which has very strong scalability to meet the different system devices’ requirements for data transmission bandwidth. Besides, the shorter PCI-E card can be inserted into the longer PCI-E slot in an application, and the PCI-E interface can also support hot-pluggable, which is considered a milestone in the industry.

 

The PCI Express standard defines link widths of ×1（250MB/s）, ×2, ×4, ×8, ×12, ×16 and ×32. But according to the current status of PCI-E, PCI-E x1 and PCI-E x 16 are two mainstream specifications. At the same time, many chipset manufacturers have added PCI-E X1 to the list of the South Bridge chip, and  PCI-E X16 to the North Bridge chip. Apart from its high data transfer rate, each physical footprint of PCI-E connectors can achieve more bandwidth than the conventional I/O specification since PCI-E transfers data through serial port data packets. Thus, this can reduce production cost and minimize the size of PCI-E devices. In addition, PCI-E also supports advanced power management, hot swapping, data synchronous transmission, and bandwidth optimization for priority data transmission.

 

7. Different Versions for PCI-E Spec

 

● PCI Express 1.0

In 2003, PCI-SIG introduced PCIe 1.0a, with a per-lane data rate of 250 MB/s and a transfer rate of 2.5 Giga transfers per second (GT/s). Since each byte is 10 bits (1 start bit, 8 data bits, and 1 end bit), the transmission rate is 2.5G/10=250MB/S (250 megabytes per second). By this, it can be calculated that the unidirectional transmission rate of PCI-E 16X is 250MB/S*16=4GB/S, and the bidirectional transmission rate is 8GB/S.

 

● PCI Express 2.0

PCI-SIG announced the availability of the PCI Express Base 2.0 specification on 15 January 2007. PCI-E 1X (2.0 standard) specified a single-direction 5G baud rate for transmission. Since each byte is 10 bits (1 start bit, 8 data bits, and 1 end bit), the unidirectional transmission rate is 5G/10=500MB/S (500 megabytes per second). Through this, it can be concluded that the unidirectional transmission rate of PCI-E 16X (2.0 standard) is 500MB/S*16=8GB/S, the bidirectional transmission rate is 16GB/S, and the ship speed rate of PCI-E 32X (2.0 standard) is 32GB/S.

 

● PCI E 3.0 

In August 2007, PCI-SIG announced that PCI Express 3.0 would carry a bit rate of 8 Giga transfers per second (GT/s). PCI-E 1X (3.0 standard) uses a unidirectional 10G baud rate for transmission. Since each byte is 10 bits (1 start bit, 8 data bits, and 1 end bit), the unidirectional transmission rate is 10G/10=1000MB/S (1000 megabytes per second). Therefore, we can infer that the single-direction transmission rate of PCI-E X16 (3.0 standard) is 1000MB/S*16=16GB/S, and the bidirectional transmission rate is 32GB/S, the bidirectional transmission rate of PCI-E X32 (3.0 standard) is up to 64GB/S.

∆ Different PCIe Specs: From PCI to PCIe 6.0

● PCI-E 4.0

PCI-SIG preliminarily announced PCI Express 4.0 On 29 November 2011, providing a 16 GT/s bit rate that doubles the bandwidth provided by PCI Express 3.0. Therefore, the rate of 16-channel bidirectional transmission can theoretically reach 512Gb/s, that is, 64GB/s. In addition, the PCI-E 4.0 standard will optimize storage devices with PCI-E interfaces, such as PCI-E hard disk drives(HDD) and PCI-E RAID cards, to capitalize on the low-latency advantages of the PCI-E bus.

 

PCI E 4.0 specs also introduced OCuLink-2, an alternative to Thunderbolt promoted by Intel. PCI-E OCuLink is developed based on PCI-E 3.0 and will use copper cables as the connection medium, providing a minimum connection rate of 8Gb/s (PCI-E 3.0 x1) and a maximum of 32Gb/s (PCI-E 3.0 x4).

 

● PCI-E 5.0

As PCIe 5.0 increased the signal rate to 32GT/s, the signal rate of the Ethernet device had reached 56Gbps, and it was transiting towards 112Gbps. In terms of data transfer rate, the measuring equipment nowadays can totally meet the measuring demand for PCIe 5.0 data signal. In fact, PCIe 5.0 signal is modulated by NRZ, while the 56Gbps Ethernet signal is by the PAM4 technique and the fundamental frequency.

 

8. Link Speeds and Bandwidth Capabilities for Common PCIe Slots

The following table shows the data transfer rate under various standards and different bit widths.

∆ PCI Express Versions and Bandwidths 

 

The figure below highlights the one-way bandwidth/data transfer rate specified in various PCIe spec versions.

∆ Bandwidths of x1, x4, x8, x16  PCIe Slots

 

From the table and figure, it can be concluded that PCIe doubles its bandwidth every 3 years.

∆ Development and Prediction of PCIe Actual & I/O Bandwidth 

 

Conclusion

PCI Express operates in consumer, server, and industrial applications, as a motherboard-level interconnect (to link motherboard-mounted peripherals). PCIe evolved from PCI born in 1992 to the current PCIe 5.0. At present, the PCI-E slot has become the main expansion slot on the motherboard. In addition to the application in graphics cards, PCI-E slots can also be used in hardware such as independent sound cards, independent network cards, USB 3.0/3.1 interface expansion cards, and SSDs.